1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly to a metal-insulator-metal (MIM) capacitor that can be used with an interconnect structure containing conductive wiring.
2. Background of the Invention
In the semiconductor industry, high performance capacitors are in great demand since such capacitors are essential for numerous applications, including, for example, RF and microwave. High performance capacitors have greater densities than a conventional capacitor, which leads to a reduction in chip size. Metal-insulator-metal (MIM) capacitors that are formed above back-end-of-the line (BEOL) metallurgy are also known.
For example, there are several existing schemes for integrating MIM capacitors with Cu interconnects. The current working scheme employs three masks for the fabrication of the MIM capacitor and TiN films are employed as the upper and lower electrode of the MIM capacitor. Because of the high resistivity associated with TiN electrodes, the prior art schemes typically exhibit high parasitic series resistance which strongly limits the performance of the devices, especially at higher frequency.
In some prior art applications, a thin layer of Al was added to the Ti stack in order to reduce this series resistance. This solution is not viable because of the severe roughness issues of an Al layer. Roughening of the bottom plate would limit the reliability of the MIM capacitor.
As the semiconductor industry introduces thinner and more exotic films into their capacitor structures embedded in interconnect layers that have higher capacitance density, the MIM capacitor functionality and reliability are diminished because the roughness causes early breakdown of the MIM capacitor dielectric by dielectric stress and field concentration. Moreover, most prior art integration schemes include an extra mask for assisting alignment of the MIM capacitor masks to the underlying metal level.
Additionally, it is highly desirable to enable higher capacitance density to reduce planar space usages by MIM capacitors, which can run into millions of square microns adding chip area and cost.
In view of the drawbacks with the prior art mentioned above, there is a need for providing an inexpensive method of fabricating higher performance, higher capacitance density MIM capacitors that can be integrated into an interconnect scheme.